In material evaluation, you must understand the knowledge of chip testing

As a hardware engineer, I need to evaluate the selection of chips in the early stage of development. For the vast majority of integrated manufacturers, they are unable to test the chip level capability and can only refer to the specifications on the datasheet to select the type. However, this process is very risky for projects with large output. This is because we ignore the impact of factors other than the chip specification on the circuit (this effect is generally unpredictable circuit failure, which can seriously reduce the yield of the product).

 

The purpose of chip testing is to eliminate failed and potential failed chips during the design and production process to prevent the flow of defective products to customers. Therefore, during the selection, we need to increase the evaluation of chip test level. Through the communication with the original factory and the closed test factory, we can obtain the key parameters and indicators of chip design verification, process and technology detection, wafer testing, and chip finished product test stage for comprehensive evaluation.

In the final product test of the chip, we are most concerned about the FT test.

FT test is a packing-level test, because it may cause partial circuit failure or parameter drift of the chip in the manufacturing process. Generally speaking, FT test in a broad sense is carried out by importing the corresponding test program through ATE (automatic test equipment) to test the chip, which will be shipped to customers after passing the ATE test. However, for customers with high requirements, after the ATE test is completed, SLT test, also known as bench Test, is usually required. SLT test is more rigorous than FT test, and it is usually Function Test to test whether the function of specific modules is normal. Of course, SLT test is usually more time-consuming than FT test, so it can only be sampling test.